1. Field of the Invention
This invention relates to computer memory systems, and, more particularly, to arrangements for selectively varying the length of control signals used in a computer memory arrangement.
2. History of the Prior Art
In a conventional computer memory system utilizing dynamic random access memory (DRAM) elements, any particular memory position is accessed by providing a row address and a column address with corresponding row address strobe and column address strobe signals each occurring at a particular time and having a particular length sufficient to select the memory position for the particular mode of operation and for the particular type of memory element being used.
Any particular memory system may be constructed of DRAM elements (or VRAM elements) all capable of switching at a particular switching speed such as 150 nanoseconds, 120 nanoseconds, or 80 nanoseconds. In the memory system any particular computer, it is desirable to be able to utilize DRAM elements having different switching times. To utilize DRAMs having different switching times in the same memory system, the control pulses such as the row address strobe and the column address strobe must therefore either be sufficiently long and occur at sufficient intervals that they may be utilized with the slowest switching DRAM elements expected to be used with the system or the system must be somehow capable of switching the times and intervals between such control pulses in some manner to match the particular switching elements to be used. If the control pulses and intervals therebetween are selected to be long enough to handle the slowest switching memory elements, then the system will run at a relatively slow speed even with memory elements capable of switching at much higher speeds. To obviate this problem, it is desirable to be able to reprogram the memory controller to take advantage of the faster access time if faster memory is inserted into the system.
Even a memory system capable of using only memory elements which operate at a single speed, may be made substantially faster if its control signals may be programmed to match the speeds of the particular modes of operation. For example, a read cycle and a write cycle may take entirely different times to accomplish. A read cycle and a page read cycle (one in which the same row address is used for adjacent memory positions so that a new page need not be addressed) should take different times to accomplish. However, unless the control signals may be varied to fit the length of the these particular modes of operation, the differences in speed available to the different modes will not in practice be carried through to the operation of the machine.
For these reasons, attempts have been made to provide programmable length control signals for effecting the operation of computer memory systems. Programmable length control signals have been realized to some extent, but the arrangements provided to date have been able to program such memory signals to select only between control signals which both begin and end on a single edge of a clock pulse (the rising edge). For this reason, the length of control pulses and the intervals therebetween have not been optimized both to match the switching times of the memory elements where those switching times may vary from unit to unit and to match the particular modes of operation being practiced by the machine.